The ability to conduct high-speed data communications between relatively remote data processing systems and associated subsystems is currently a principal requirement of a variety of industries and applications, such as business, educational, medical, financial and personal computer users. Moreover, it can be expected that present and future applications of such communications will continue to engender more such systems and services. One technology that has attracted particular interest in the telecommunication community is digital subscriber line (DSL) service. DSL technology enables a public service telephone network (PSTN) to use existing telephone copper wiring infrastructure to deliver a relatively high data bandwidth digital communication service, that is selected in accordance with expected data transmission rate, the type and length of data transport medium, and schemes for encoding and decoding data.
FIG. 1 is a reduced complexity diagram of the general architecture of a DSL system, having mutually compatible digital communication transceivers 1 and 3, respectively installed at relatively remotely separated ‘west’ and ‘east’ sites 2 and 4, and coupled to a communication link 10, such as a twisted pair of an existing copper plant. One of these transceivers, for example, the west site transceiver 1, may be installed in a digital subscriber line access multiplexer (DSLAM) 6 of a network controller site (such as a telephone company central office (CO)). The DSLAM is coupled with an associated network backbone 5 that provides access to a number of information sources 7 and the Internet 8. As such, the west site transceiver 1 is used for the transport of digital communication signals, such as asynchronous transfer mode (ATM)-based packetized voice and data, from the central office site 2 over the communication link 10, to an integrated access device (IAD) serving as the DSL transceiver 3 at the east end of the link, and may be coupled with a computer 9 at a customer premises, such as a home or office.
An integrated access device is used to consolidate digitized data, voice and video traffic over a common wide area network (WAN) DSL link. This digitized voice stream may be encoded as mu-law or a-law voice samples, or it may comprise digitally encoded voice samples from an integrated services digital network (ISDN) phone. These digitally encoded voice samples are typically encapsulated in accordance with packet or cell protocol for transport over the network (for example, using voice over asynchronous transfer mode (ATM) or voice over internet protocol (IP)).
Because digital subscriber line transport systems of the type shown in FIG. 1 are customarily designed to provide as efficient use of the available bandwidth as possible, their major concern lies with parameters of the communication link, while secondarily they might address what takes place at an end user site that is interfaced with the link. At data terminal site, on the other hand, it is the performance of the data processing system that receives the principal emphasis. When these two subsystems are interfaced with one another, overall throughput efficiency may depend upon how well each is able to handle events that are characterized by protocols and data formats employed by the other subsystem.
One area where this problem occurs involves the manner in which data is encapsulated for transport over the communication link versus the way data is processed at the terminal site. Where the terminal site employs an embedded reduced instruction set computer (RISC)-based, data processing subsystem (such as but not limited to a 32-bit processor), it may encounter substantial throughput delays that result from an incoming (packetized) data stream creating unaligned accesses to memory. An unaligned memory access occurs when a central processing unit (CPU) read/load or write/store instruction references an address in memory, that does not conform to the natural or inherent alignment of the memory size, such as a 32-bit access for a (32-bit) word access, and a 16-bit access for a half-word access.
In a 32-bit system, a word access will be properly aligned with the natural memory addressing scheme, provided that the least two significant bits of the address are zero; for a half-word access to be naturally aligned, the least significant bit must equal zero. To illustrate this situation, FIG. 2 shows a reduced complexity diagram of a 32-bit memory 200 of arbitrary storage capacity, as may be used to store an instruction set. Memory 200 is comprised of successive rows 201, 202, 203, etc. of four bytes each, with a respective ith row being addressable by means of an associated N bit hexadecimal address code 210-i. 
In order to step through the instruction set stored in respective rows of the memory, in compliance with its natural boundaries, the processor's program counter will be incremented four bytes at a time, beginning with the address code 0000hex, which addresses the first row 201 as a four-byte entity encompassing all 32 bits (0–31). To access successive 32 bit words (the next word being that stored in the second row 202), the program counter is incremented to the address code 0004hex, and so on, through codes 0008hex, 000Chex, 0010hex, etc., each of which has its two least significant bits equal to zero, so as to conform with the natural boundaries of the 32-bit space that defines each row of memory.
In the course of incrementing the program counter, the processor may encounter an instruction that contains an access (read or a write) to a region of memory which overlaps adjacent memory locations (e.g., two consecutive rows for the 32-bit wide memory of the present example). FIG. 3 shows an example of such an unaligned address condition, for a word address to a 32-bit entity 300 (comprised of successive bytes 301, 302, 303 and 304), the first byte 301 of which corresponds to the second byte of row j and the fourth byte 304 of which corresponds to the first byte of adjacent row j+1. FIG. 4 shows a similar overlap situation for half-word address to a 16-bit entity 400 (comprised of bytes 401 402), the first byte 401 of which corresponds to the fourth byte of row j and the second byte 402 of which corresponds to the first byte of adjacent row j+1.
As pointed out above, such boundary-crossing or unaligned memory accesses will occur where a memory address code ends in anything other than 00-binary for a word access, or anything other than 0-binary for a half-word access. In some processing systems, upon the occurrence of such an unaligned access, a fatal error is declared and the system is reset. While a reset may be acceptable in a system that processes archival data, it cannot be tolerated in a digital data communication network, where real time processing and throughput are required.